A flash memory device is programmable non-volatile semiconductor memory device. The flash memory device is used in many semiconductor devices including universal serial bus (USB) flash devices for data storage and transfer. A field effect transistor including a floating gate and a control gate comprises a core of a unit cell of the flash memory device. Continual scaling of the unit cell of the flash memory has led to increased memory density for semiconductor chips including the flash memory device.
A non-volatile memory cell such as flash memory using a floating gate to conduct programmability suffers a non-planarization problem. Specifically, the presence of two gate electrodes, i.e., a control gate and a floating gate, makes the integration of a flash memory device with other field effect transistors comprising a logic circuit, such as a peripheral circuit that supports the operation of an array of flash memory cells, difficult. This is because the floating gate element which is added to the flash memory device causes the physical structure of the flash memory device to be higher than other regular complementary metal-oxide-semiconductor (CMOS) devices that do no include the floating gate element. The floating gate is needed only for the flash memory device, and is not needed for logic transistors. Formation of a material layer for the floating gate induces differences in material stack heights between the flash memory array region and a logic device region, inducing a significant variation in topography of the top surface of the material stacks that need to be lithographically patterned.
Surface topography, i.e., variations in the height of a surface, reduces lithographic processing window because all lithography tools have a finite depth of focus, i.e., a vertical range of height that produces a well defined lithographic image. Surface topography effectively reduces the usable focus of depth of a lithography tool because the height of the bottom surface of the photoresist varies with the surface topography of an underlying structure. The inherent non-planar surface topography in a semiconductor chip including flash memory devices and regular CMOS devices results in higher processing cost, lower reliability, a larger chip size, and/or poor performance. In order to scale down a semiconductor chip in a manufacturable manner, the surface topography of a semiconductor chip needs to be minimized during the processing steps in manufacturing.
Prior art methods for reducing surface topography in planar flash memory cell structures have been known, each with its own drawbacks. For example, U.S. Pat. No. 6,424,001 to Forbes et al. discloses methods for making a flash memory device having a very thin vertical floating gate structure located on a sidewall of a vertical transistor. Unconventional processing steps are required for formation of the vertical transistor, and integration with standard CMOS devices is not straightforward.
U.S. Pat. No. 6,809,372 to Gambino et al. discloses a flash memory cell structure employing a sidewall floating gate. Because the floating gate of this flash memory cell structure is located on a sidewall of the device, the area of this flash memory cell structure is greater than the area of a conventional stacked floating structure employing a comparable gate length.
U.S. Pat. No. 7,064,377 to Hagemeyer et al. discloses a flash memory cell having a buried floating gate. The programmable read-only memory cell comprises a floating gate located in a trench. An epitaxial channel layer formed over the floating gate. This flash memory cell structure requires many processing steps that do not belong to conventional CMOS processing steps, which increase manufacturing cost.
A similar approach is disclosed in U.S. Pat. No. 6,052,311 to Fu, in which a floating gate is buried underneath the channel of a field effect transistor. In addition to requiring many additional processing steps, the trench may cause high-stress in the substrate. Further, a high overlapping capacitance between source/drain junctions and the floating gate element may degrade performance of the flash memory cell.
In view of the above, there exists a need for a flash memory device structure that provides a planar surface for lithographic patterning of gate structures including the floating gate, and methods of manufacturing the same economically and without incurring an excessive number of additional processing steps.